The invention relates to microcomputers, computer systems and methods of operating such.
Microcomputer chips may include a CPU with a plurality of other modules as well as a memory interface on the same chip. The CPU as well as other modules may need to carry out memory access operations in order to effect read and write operations. Furthermore, some modules on the chip may need to generate interrupt requests to vary to routine operated by another device on the chip and in some cases it may be necessary to provide control commands to which an on-chip CPU must respond.
It is an object of the present invention to provide an improved computer system and method of operating a computer system for distributing memory access requests and other requests on a chip.
The invention provides a computer system including an integrated circuit chip with an address and data. path interconnecting a plurality of on-chip devices including at least one CPU, at least one module and a memory interface, (a) said module having packet generating circuitry responsive to an event to generate an event request packet including a destination address, (b) said CPU having event logic to decode the packet and identify the request of the packet, and circuitry to generate addressed memory access packets, and (c) said address and data path being used for distribution of both event request packets arid memory access packets.
Preferably both said module and said CPU each include packet generating circuitry operable to generate both event request packets and memory access packets for distribution on the common address and data path.
Preferably the packet generating circuitry is responsive to receipt of an event request packet to generate an addressed response bit packet for distribution on said address and data path.
Preferably the packet generating circuitry of a module includes means to indicate the address of the destination for the packet as well as the address of the module acting as a source of the packet.
Preferably the packet generating circuitry is responsive to receipt of an event request packet to determine from the packet a source address of the packet and to generate a response packet using said source address as the destination indicator for the response packet.
The system may include an on-chip memory, said memory interface providing connection between said address and data path and said on-chip memory.
The system may include an off-chip memory, said chip having an external memory interface connected to said off-chip memory and to said address and data path.
The packet generating circuitry of said module may be arranged to generate an event request packet forming an interrupt request with a priority indicator and said event logic of the CPU includes comparator circuitry for comparing priorities of event request packets received with the priority of any current CPU activity.
The packet generating circuitry of said module may be arranged to generate an event request packet in the form of a control packet for control command to the CPU.
Preferably a plurality of modules are provided on chip, each having packet generating circuitry for generating event request packets, at least one module being arranged to generate event packets in the form of prioritised interrupt requests and at least another module being arranged to generate event request packets in the form of control packets for the CPU.
Preferably said address and data path includes at least one on-chip bus arranged to distribute said packets in bit parallel format.
Preferably said integrated circuit chip includes at least one external port for off-chip connection, said port including bit format translation circuitry to convert on-chip packets of bit parallel format to a less parallel format for transmission off-chip.
The invention also provides a method of operating a computer system comprising an integrated circuit chip with an address and data path interconnecting a plurality of on-chip devices including at least one CPU, at least one module and a memory interface, which method comprises detecting an event at a module, generating an event request packet with a destination address, distributing the request packet on the address and data path to the destination, decoding the packet at the destination to identify the nature of the request, said method further including generating addressed memory access packets for memory read and write operations, said memory access packets and said event request packets being distributed on the same address and data path.
Preferably event request packets are generated for distribution on the address and data path to the CPU, which event request packets are in the form of prioritised interrupt requests.
Preferably event request packets are generated for distribution on said address and data path to the CPU, at least some of said event request packets being in the form of control command packets to which the CPU must respond on receipt of the packet.